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David Lenfesty e850430a8c """Finished""" base RV32I instructions 
Still a few base instructions to go, but those are waiting on the
privileged implementation. My game plan:

- implement privileged spec (M-only), adding way to handle traps
- finish implementing last of the base instructions
- add in exceptions that have been ignored in all instructions
- clean up main memory interface, mmaybe add some caching, at least some
  instruction cache.
2021-05-29 19:42:11 -06:00
riscv-tests@09cfdaacd9 """Finished""" base RV32I instructions 2021-05-29 19:42:11 -06:00
.gitignore Started RV32I core, theoretically done integer immediates 2021-05-23 22:16:14 -06:00
.gitmodules """Finished""" base RV32I instructions 2021-05-29 19:42:11 -06:00
core.py """Finished""" base RV32I instructions 2021-05-29 19:42:11 -06:00
instruction_decoder.py """Finished""" base RV32I instructions 2021-05-29 19:42:11 -06:00
opcodes.py Started RV32I core, theoretically done integer immediates 2021-05-23 22:16:14 -06:00
README.md """Finished""" base RV32I instructions 2021-05-29 19:42:11 -06:00
regfile.py Started RV32I core, theoretically done integer immediates 2021-05-23 22:16:14 -06:00

README.md

runt

A small, underperforming RV32I core, written in nMigen.

I want to get it to the point where I could actually use it in a design, but I doubt it will have any practical use, especially when compared to a VexRiscV or picorv32 core.

This is my first CPU, and I also somewhat intentionally didn't look at any resources, so it will likely be full of questionable design decisions that anyone with any experience would have avoided.

Milestones

  • Full RV32I implementation, able to run code in simulation (not verified working correctly at this point)
  • Full coverage with riscv-tests, verified working.
  • Integrated with some hardware to make an """SoC""", running on my Arty A7
  • Full coverage with riscv-formal
  • (Maybe...) work on improving performance, add caching/prefetch, pipeline it, etc.