David Lenfesty
e850430a8c
Still a few base instructions to go, but those are waiting on the privileged implementation. My game plan: - implement privileged spec (M-only), adding way to handle traps - finish implementing last of the base instructions - add in exceptions that have been ignored in all instructions - clean up main memory interface, mmaybe add some caching, at least some instruction cache.
20 lines
832 B
Markdown
20 lines
832 B
Markdown
# runt
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A small, underperforming RV32I core, written in nMigen.
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I want to get it to the point where I could actually use it in a design, but I doubt it will have
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any practical use, especially when compared to a VexRiscV or picorv32 core.
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This is my first CPU, and I also somewhat intentionally didn't look at any resources,
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so it will likely be full of questionable design decisions that anyone with any experience
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would have avoided.
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## Milestones
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- [ ] Full RV32I implementation, able to run code in simulation (not verified working correctly at
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this point)
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- [ ] Full coverage with riscv-tests, verified working.
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- [ ] Integrated with some hardware to make an """SoC""", running on my Arty A7
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- [ ] Full coverage with riscv-formal
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- [ ] (Maybe...) work on improving performance, add caching/prefetch, pipeline it, etc.
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