david

david closed issue david/new-sonar#2

2023-06-03 11:59:04 -06:00

Get embassy up and running

david closed issue david/new-sonar#4

2023-06-03 11:58:19 -06:00

Start RTL test infrastructure

david closed issue david/new-sonar#5

2023-06-03 11:58:00 -06:00

Create LiteEth rust driver

david commented on issue david/new-sonar#21

2023-06-03 11:57:51 -06:00

Create a timer peripheral

LiteX does this

david closed issue david/new-sonar#21

2023-06-03 11:57:51 -06:00

Create a timer peripheral

david commented on issue david/new-sonar#16

2023-06-03 11:57:40 -06:00

Create interrupt controller

Moved to LiteX

david closed issue david/new-sonar#16

2023-06-03 11:57:40 -06:00

Create interrupt controller

david closed issue david/new-sonar#12

2023-06-03 11:57:28 -06:00

Create data acquisition module.

david commented on issue david/new-sonar#13

2023-06-03 11:57:21 -06:00

Add proper data selection to RAM module

Finished in Amaranth and also using LiteX now

david closed issue david/new-sonar#13

2023-06-03 11:57:21 -06:00

Add proper data selection to RAM module

david closed issue david/new-sonar#17

2023-06-03 11:57:03 -06:00

Define what should be available for run-time configuration.

david commented on issue david/new-sonar#17

2023-06-03 11:57:01 -06:00

Define what should be available for run-time configuration.

Done: constraints set by peak detector implementation.

Set the 4 peak detector values, gain, center frequency, and enable/disable capture.

david closed issue david/new-sonar#15

2023-06-03 11:56:17 -06:00

Select ethernet communication protocol

david commented on issue david/new-sonar#15

2023-06-03 11:56:11 -06:00

Select ethernet communication protocol

TCP for both. Config channel will use simple packet thing.

Data channel will have a start sequence that can't exist in data, and will only TX from FPGA to ROS.

Only one connection allowed…

david commented on issue david/new-sonar#18

2023-06-03 11:54:46 -06:00

Add debug access to Minerva core

Moved to LiteX, so using vexriscv. Could add a debug port I think, but I'm past bringup hell anyways, and I have defmt for nice tracing, so will ignore.

david closed issue david/new-sonar#18

2023-06-03 11:54:46 -06:00

Add debug access to Minerva core

david commented on issue david/new-sonar#22

2023-06-03 11:54:04 -06:00

Create a rust driver for the timer peripheral

Note: using LiteX timer now, I have something functioning, probably want to clean it up though before I close this

david commented on issue david/new-sonar#36

2023-06-03 11:52:22 -06:00

Fix documentation of I2C device in amlib

Not using amaranth/amlib anymore

david closed issue david/new-sonar#36

2023-06-03 11:52:22 -06:00

Fix documentation of I2C device in amlib

david commented on issue david/new-sonar#39

2023-06-03 11:52:06 -06:00

Create clock generation module

LiteX has this, moved back to LiteX