Commit Graph

116 Commits

Author SHA1 Message Date
833db12d58 fw: make build script return with error code so it can be scripted 2023-04-22 17:41:51 -06:00
a864da5354 fw: eth testing and debug process 2023-04-22 13:39:32 -06:00
29ec5a8a43 tracking a couple files I missed 2023-04-16 11:06:02 -06:00
9b49f1184e fw: more progress for ethernet, unable to read data 2023-04-15 22:43:52 -06:00
3b2af908c7 gw: get LiteEth working!
Link comes up! Not working fully, but that could be firmware too
2023-04-15 18:11:16 -06:00
1204be4fa0 fw: mostly implement smoltcp driver? unsure if it works 2023-04-15 17:06:59 -06:00
d207181ef5 gw: increase ROM size 2023-04-15 13:00:06 -06:00
005a053624 fw: testing and fix a couple blocking bugs! 2023-04-15 12:59:54 -06:00
b7b556f6d2 firmware: i2c work, not finished 2023-03-25 15:21:54 -06:00
60e468340c gateware: make i2c actually read status bits 2023-03-25 15:21:35 -06:00
241cb72553 gateware: fix RAM and ROM issues 2023-03-25 15:21:03 -06:00
ac746a8c5a firmware: add I2C 2023-03-24 20:54:59 -06:00
bf482e740d firmware: add UART 2023-03-24 20:54:50 -06:00
a05af8739c gateware: fix UART and connections 2023-03-24 20:54:05 -06:00
348f6d5ba6 gateware: fix sizing and add size configurability 2023-03-24 20:53:37 -06:00
96dabe013a gateware: add UART to CSR 2023-03-24 17:42:27 -06:00
32fb8383d1 just create a local platforms folder instead of a forked amaranth_boards 2023-03-24 17:33:13 -06:00
f846cc1fab gw: get i2c up and running (ish) in simulation 2023-03-21 20:09:04 -06:00
ea32a00b68 fw: write common read/write function 2023-03-05 19:37:54 -07:00
4e7c9984d7 add vscode settings to make rust-analyzer work 2023-03-05 19:19:45 -07:00
26389576d5 fw: first attempt at writing a packet
Unsure if this is working, not sure if I have the tools to even know if
it does.

I could spend the time to actually write the packet by hand, or I could
probably spend ~2x the time and get smoltcp up.

Either way, the HW is validated, I am bringing up a link, I can talk to
LiteEth, so past here is driver stuff
2023-03-05 12:58:18 -07:00
925a605af9 hw: revision A gerbers 2023-03-05 11:53:18 -07:00
fdf3ddeb4a hw: added some notes on RevA bringup issues 2023-03-05 11:52:41 -07:00
54ac22429e add jtagdap submodule for now
(need to update it to use amaranth to do debug in minerva)
2023-03-05 11:52:16 -07:00
6ef410786e fw: moving forward a bit 2023-03-05 11:48:08 -07:00
cc763a3e9b requirements.tx: amaranth-community-unofficial -> amaranth-farm 2023-03-05 11:47:09 -07:00
8d00e15835 gateware: fix dumb mistakes
Bus widths should now all be correct. (addresses and sizes in amaranth
take into account the granularity selection, so granularity acts like
two extra bits on the bus address line)

Also don't ignore a warning about undriven resets. Turns out that can
gate *everything* off in your design.
2023-03-05 11:43:59 -07:00
60b7b485da fw: start janky ethernet bringup testing 2023-03-04 12:42:22 -07:00
a970a0154b hardware: add some bringup notes for rev A 2023-03-04 12:42:15 -07:00
8b19464608 gateware: propogate MDIO signal correctly w/o IOBUF
This was causing my nextpnr crash. I really do need to figure out how to
do this in a less hacky way. Or even just make it more explicit that I
am doing this for a reason.
2023-03-04 12:41:16 -07:00
6e89c0d837 gateware: actually integrate ethernet 2023-03-04 10:54:43 -07:00
56d13a0e77 gateware: add PLL and generate two clocks
TODO is make a proper clock gen object, maybe it could run ecppll by
itself?
2023-02-25 12:56:09 -07:00
1b39199df3 gateware: generate PLL with 'ecppll' 2023-02-25 12:24:03 -07:00
fe379be39b gateware: saving some state again 2023-02-18 11:56:39 -07:00
5595c7d113 gateware: import basic instance of LiteEth
more config to do, need to fully hook everything up, but it's a start
2023-02-07 21:00:38 -07:00
0bf4fb5c1b gateware: test out UART, had to fix SR flags 2023-02-04 14:40:05 -07:00
c3f62c271c hardware: export first production gerbers 2023-02-04 13:11:54 -07:00
52012dc4ad gateware: saving some WIP on UART 2023-02-04 12:04:01 -07:00
71ca5a31be gateware/i2c: flesh out full R/W transaction in test 2023-01-30 10:09:28 -07:00
f0683e684c gateware: Properly migrate I2C test into my new framework 2023-01-29 21:32:56 -07:00
9997db0ac8 gateware: create vcd_out directory by default 2023-01-29 20:41:17 -07:00
ad3be1f4c7 gateware: put in some testing infrastructure
It's pretty hacky tbh, probably should be improved.

But also this will probably scale with the entire project so I don't
care.
2023-01-29 20:38:32 -07:00
490b92b1fd gateware: first work with I2C peripheral
Basic details seem to be working, and I'm on my way with testing.

Next steps:
- Build out more local testing utilities
- Build out unittest infrastructure
- Flesh out more tests to verify operation
2023-01-29 16:54:29 -07:00
6a4a9784e3 gateware: fix some issues introduced with cleanup 2023-01-29 16:54:14 -07:00
dbf81c4baf finished first revision of hardware! 2023-01-28 13:29:56 -07:00
50a286afbe hardware: schematic should be finished, layout seems roughly solid 2023-01-25 21:44:12 -07:00
8bc0e55104 Add python dependency install instructions 2023-01-23 22:38:53 -07:00
5619482029 gateware: start spreading out into a couple modules 2023-01-23 22:32:46 -07:00
296206524c gateware: remove LiteX attempt 2023-01-23 22:28:03 -07:00
db431e7ba7 Improve top-level docs 2023-01-23 22:27:45 -07:00