7e3239700d
start playing around with sampler (not working at all, wb issues I think)
2023-06-17 15:56:11 +00:00
64fb1fd3a6
Add patch to migen to maybe fix things?
2023-06-03 16:35:39 -06:00
d691f2a649
add dockerfile so we can build
2023-06-03 15:19:32 -06:00
5b62dd300b
gw: fix synthesis
...
Still unclear what exactly this fixes, I think mostly bugs in
migen/LiteX. Not sure if it's synthesizing the memory elements for the
sampler modules either.
2023-06-03 11:44:17 -06:00
aebb3a58f0
gw: add ADC2-4 pinouts and update changed pins
2023-05-27 13:30:17 -06:00
8e6e483f92
gw: switch to strobe-style control bits for controller
2023-05-27 13:20:26 -06:00
0e3328aac1
gw: add some end to end unit tests for sampler controller
2023-05-27 12:08:34 -06:00
e624d82742
gw: minor fixes for correct controller operation
2023-05-27 12:08:12 -06:00
627550840c
gw: add skipping test suites
2023-05-27 11:03:18 -06:00
942dba8ea3
gw: fix CircularBuffer test
...
with_wb = True overrides the rd_addr, which broke the test. Just had to
disable that param and the test was correct again
2023-05-27 11:02:31 -06:00
1ab88bb698
gw: more peak detector unit tests
2023-05-27 10:36:48 -06:00
0185d81d46
gw: minor tweaks to peak detector to improve behaviour
2023-05-27 10:36:46 -06:00
1d8c9ca224
gw: Start testing peak detector, and fix a bug!
2023-05-27 10:36:42 -06:00
f6d3868273
re-arrange things and start a simple test manager
2023-05-13 09:49:58 -06:00
2faf509506
gw: implement sampler controller with peak detector
...
Mostly untested, will need testing with simulated waveforms to validate
correctness.
2023-05-07 15:15:18 -06:00
39b5dd7193
gw: finish CDC sampler module
...
Just need to hook this into the FIFO I made before, and write all the
peak detection, triggering, and trigger enable logic, + hook everything
into a single wishbone address space.
2023-04-23 20:45:57 -06:00
0bf6c2336c
gw: finish testing sampler and fix a couple bugs
2023-04-23 20:08:17 -06:00
dc762bca8d
gw: start writing circular buffer
2023-04-23 19:46:23 -06:00
c5db01c70f
gw: fix eth.py addressing issues
2023-04-22 18:38:26 -06:00
c0b293e0c7
gateware: move back to LiteX
...
Had too many issues with integrating LiteEth. I put my FW into a LiteX
SoC and it worked, so I migrated back. With the knowledge I gained doing
Amaranth I could fix the issues I had adding a wishbone slave device
pretty easily.
2023-04-22 18:35:13 -06:00
29ec5a8a43
tracking a couple files I missed
2023-04-16 11:06:02 -06:00
3b2af908c7
gw: get LiteEth working!
...
Link comes up! Not working fully, but that could be firmware too
2023-04-15 18:11:16 -06:00
d207181ef5
gw: increase ROM size
2023-04-15 13:00:06 -06:00
60e468340c
gateware: make i2c actually read status bits
2023-03-25 15:21:35 -06:00
241cb72553
gateware: fix RAM and ROM issues
2023-03-25 15:21:03 -06:00
a05af8739c
gateware: fix UART and connections
2023-03-24 20:54:05 -06:00
348f6d5ba6
gateware: fix sizing and add size configurability
2023-03-24 20:53:37 -06:00
96dabe013a
gateware: add UART to CSR
2023-03-24 17:42:27 -06:00
32fb8383d1
just create a local platforms folder instead of a forked amaranth_boards
2023-03-24 17:33:13 -06:00
f846cc1fab
gw: get i2c up and running (ish) in simulation
2023-03-21 20:09:04 -06:00
54ac22429e
add jtagdap submodule for now
...
(need to update it to use amaranth to do debug in minerva)
2023-03-05 11:52:16 -07:00
8d00e15835
gateware: fix dumb mistakes
...
Bus widths should now all be correct. (addresses and sizes in amaranth
take into account the granularity selection, so granularity acts like
two extra bits on the bus address line)
Also don't ignore a warning about undriven resets. Turns out that can
gate *everything* off in your design.
2023-03-05 11:43:59 -07:00
8b19464608
gateware: propogate MDIO signal correctly w/o IOBUF
...
This was causing my nextpnr crash. I really do need to figure out how to
do this in a less hacky way. Or even just make it more explicit that I
am doing this for a reason.
2023-03-04 12:41:16 -07:00
6e89c0d837
gateware: actually integrate ethernet
2023-03-04 10:54:43 -07:00
56d13a0e77
gateware: add PLL and generate two clocks
...
TODO is make a proper clock gen object, maybe it could run ecppll by
itself?
2023-02-25 12:56:09 -07:00
1b39199df3
gateware: generate PLL with 'ecppll'
2023-02-25 12:24:03 -07:00
fe379be39b
gateware: saving some state again
2023-02-18 11:56:39 -07:00
5595c7d113
gateware: import basic instance of LiteEth
...
more config to do, need to fully hook everything up, but it's a start
2023-02-07 21:00:38 -07:00
0bf4fb5c1b
gateware: test out UART, had to fix SR flags
2023-02-04 14:40:05 -07:00
52012dc4ad
gateware: saving some WIP on UART
2023-02-04 12:04:01 -07:00
71ca5a31be
gateware/i2c: flesh out full R/W transaction in test
2023-01-30 10:09:28 -07:00
f0683e684c
gateware: Properly migrate I2C test into my new framework
2023-01-29 21:32:56 -07:00
9997db0ac8
gateware: create vcd_out directory by default
2023-01-29 20:41:17 -07:00
ad3be1f4c7
gateware: put in some testing infrastructure
...
It's pretty hacky tbh, probably should be improved.
But also this will probably scale with the entire project so I don't
care.
2023-01-29 20:38:32 -07:00
490b92b1fd
gateware: first work with I2C peripheral
...
Basic details seem to be working, and I'm on my way with testing.
Next steps:
- Build out more local testing utilities
- Build out unittest infrastructure
- Flesh out more tests to verify operation
2023-01-29 16:54:29 -07:00
6a4a9784e3
gateware: fix some issues introduced with cleanup
2023-01-29 16:54:14 -07:00
8bc0e55104
Add python dependency install instructions
2023-01-23 22:38:53 -07:00
5619482029
gateware: start spreading out into a couple modules
2023-01-23 22:32:46 -07:00
296206524c
gateware: remove LiteX attempt
2023-01-23 22:28:03 -07:00
db431e7ba7
Improve top-level docs
2023-01-23 22:27:45 -07:00
